Error (10821): HDL error at count.vhd(20): can't infer register for "cnt[0..8]

[pietro11]

Ahoj dělám čítač ve vhdl ale píše mi chybu 10821
"Error (10821): HDL error at count.vhd(20): can't infer register for "cnt[0..8]" because its behavior does not match any supported register model"

nevím co s tím
muj code

entity count is
	port
	(
		clock	: in std_logic;
		load	: in std_logic;
		reset	: in std_logic;
		enable 	: in std_logic;
		q		: out integer range 0 to 256
	);
end entity;

architecture behav of count is
begin
	process (clock,load,reset,enable)
		variable cnt: integer range 0 to 256;
	begin	--rising_edge funkce pro náběžnou hranu
		if (rising_edge(clock)) then
			if reset = '1' then
				cnt := 0;
			elsif load='0' then
				cnt:= 128;
			elsif (rising_edge(enable)) then
				cnt := cnt + 1;
			end if;
		end if;
		q <= cnt;
	end process;

end behav;

 

[Codik]

imho nemuzes mit rising_edge(enable)
doporucil bych abys tam mel signal enable_prewious
kde pokud jsou hodiny das aby
enable_prewious <= enable;
a pak misto rising edge dat if (enable= '1' and enable_prewious='0') citlzvz na hranz to proste je jen na hodiny